Delay locked loops (DLL) have many uses in integrated circuits, and generally operate to form a stable output clock signal from an input clock signal. A typical DLL 10 is shown in FIG. 1. As shown, the DLL 10 derives an output clock signal (ClkOut) from an (usually external) input clock signal (ClkIn), in which the phase or delay between the two clocks can be tightly controlled. The DLL 10 comprises a variable delay line (VDL) 12 for providing a variable amount of delay to the input clock signal, and a delay model 14. As is known, the delay model 14 models delays outside of the loop, such as those provided by the input buffers 13, and other delays such as the output buffers, the clock distribution network, etc., which are shown collectively for simplicity in FIG. 1 as buffer 15.
Ignoring Tac trim circuitry 20 for the moment, the output of the delay model 14 and the input clock signal, ClkIn, are compared at a phase detector 16, which essentially determines whether one of these signals is lagging or leading the other, and seeks to bring these two phases into alignment. For example, if the output of the delay model 14 leads ClkIn, then the phase detector 16 outputs an “Up” signal, which increases the delay through the VDL 12 by moving entry point (EP) to the left in FIG. 1. (As is known, the entry point (EP) dictates the stage at which the input clock enters the VDL 12. However, and to the same effect, the entry point can also be fixed at the left most stage of the VDL 12 with the exit point out of the VDL varying to vary the delay through the VDL. For simplicity, this disclosure discusses a variable entry point instead of a variable exit point, although the technique is equally applicable to a VDL with a variable exit point). By contrast, if the output of the delay model 14 lags ClkIn, then the phase detector 16 outputs a “Down” signal to decrease the delay through the VDL 12 by moving the entry point (EP) to the right. Through this scheme, the output clock signal, ClkOut, can eventually be locked into a phase relationship with the input clock signal, ClkIn. Further details concerning the architecture and control of a variable delay line useable in a DLL can be found in U.S. patent application Ser. No. 11/608,903, filed Dec. 11, 2006, which is incorporated herein by reference in its entirety.
As alluded to earlier, trim circuitry 20 is provided to add delay into the signals being input to the phase detector 16. When the DLL 10 is used in a Synchronous DRAM (SDRAM) for example, such circuitry can be referred to as Tac trim circuitry 20, because such circuitry generally compensates for the access time (Tac) at which data output is valid relative to the external clock, ClkIn. As one skilled in the art understands, Tac is generally specified by the manufacture of the SDRAM device, and may be tailored to suit a customer's preference. Tac is also a function of processing and other variations.
The Tac trim circuitry 20 compensates for the effect of Tac in the DLL 10. So as to reduce the minimum DLL's forward-path delay, the Tac trim circuitry 20 is placed outside of the DLL's forward path, and instead is placed in front of the phase detector 16. As one skilled in the art will understand, such placement of the Tac trim circuitry 20 reduces power supply sensitivity, jitter, and power consumption.
Preferably, the Tac trim circuitry 20 is divided into individual delays 20a and 20b: delay 20a provides a delay of Tref to the buffered input clock; while delay 20b provides a delay of Tfb to the clock as fed back from the output of the VDL 12. Generally, each of these delays 20a, 20b are programmable, such as by blowing fuse links, etc. Having separate delays Tref and Tfb in the Tac trim circuitry 20 allows the Tac to be adjusted positively or negatively, which again may be desirable to suit a particular customer's requirements or to compensate for processing and/or other variations. If an increase in Tac is desired, Tref is programmed for a longer delay. If a decrease in Tac is desired, Tfb is programmed for a longer delay.
It is desirable in a synchronous DRAM to produce an output clock signal which is in phase with the input clock signal, taking into account the Tac trim adjustment. In other words, and referring to the various time delays between the input and output clock in FIG. 1, the condition in which the two clocks are appropriately synchronized is:Tvd1(ideal)+Td1+Tid+Td2=N*Tck  (Eq. 1)where N equal a positive integer, Tck equals the period of the input clock, Td1 equals the delay inherent in the buffer 13 (and any other delay prior to the DLL 10), Td2 equals the delays inherent in the buffer 15 (e.g., clock distribution circuitry, tree drivers, output latches, output drivers, etc.), Tid comprises delays inherent in entering and exiting the VDL 12, and Tvd1(ideal) equals the ideal delay through the VDL 12 to achieve a lock condition. In other words, the VDL 12 inserts enough delay so that the entire forward path of the DLL 10 is exactly an integer multiple of the clock period (N*Tck).
Note that in Equation (1), all of the time delays are generally constant, except for Tvd1, the variable delay through the VDL 12. Because of this, realization of the lock condition of Equation (1) generally requires proper setting of Tvd1, in other words:Tvd1(ideal)=N*Tck−(Td1+Tid+Td2)  (Eq. 2)
Therefore, for the DLL 10 to achieve a lock condition quickly, Tvd1 is preferably initialized to a value which satisfies the lock condition of Equations (1) and (2). This means that the entry point (EP) (or exit point if that varies) of the VDL 12 must be properly initialized so that the buffered input clock signal (from buffer 13) enters the VDL 12 at an appropriate stage.
Such initialization of the VDL 12 generally employs a measurement taken prior to useful operation of the device, which can be performed after power up of the device for example. Such a measurement is described with reference to FIG. 2, which shows the initialization circuitry portion 75 of the DLL 10. Because FIG. 2 only shows those aspects of the DLL circuitry useful during initialization, additional circuitry is shown when compared to FIG. 1, and some other circuitry not implicated during the initialization measurement (e.g., the phase detector 16) is not shown.
The DLL initialization circuitry 75 of FIG. 2 uses clock timing signals to measure Tvd1 (Tvd1(meas)), which value is then loaded into the VDL 12 to initialize it close to the ideal value (Tvd1(ideal)). The approach is similar to a stopwatch, in which one clock signal starts the timing and another clock signal stops the timing. To quickly summarize, a clock is inserted into the VDL 12 at (B). This clock is allowed to propagate through some number of stages in the VDL 12 until another clock (C) arrives at the VDL 12 and captures the ‘distance’ (i.e., number of stages) that clock (B) has traveled in the VDL 12. In this sense, the clock (B) is the ‘start’ signal and the clock at (C) is the ‘stop’ signal.
This process is now discussed in further detail. The ‘start’ clock pulse begins at point (A). Because the multiplexer (MUX) control signal 30′ of MUX 30 is set by DLL initialization logic 50 to choose the bottom input through the entirety of the measurement process, the ‘start’ clock pulse does not (yet) enter the VDL 12. (Note that the control signal 30′ for MUX 30 will choose the top input during normal operation, i.e., after initialization). Instead, the ‘start’ clock pulse passes through the Tref delay 20a, where it encounters another MUX 32. This MUX's control signal 32′ initially passes the top input, and now the ‘start’ clock pulse passes to the VDL 12. (Again, MUX 30 allows the bottom input to pass). Because the initialization logic 50 initially sets the EP to a minimum values, Tvd1=0, and instead the ‘start’ clock pulse encounter only the VDL 12's intrinsic delays (Tid).
Thereafter, the ‘start’ clock pulse passes through the delay model 14, though Tfb delay 20b, where it triggers Flip-Flop 22a (at which point the pulse is converted to an edge). At this point, the control 32′ for MUX 32 now chooses the just-latched ‘start’ edge (i.e., the bottom input), and passes it to point (B). At this point, the MUX 30 allows this ‘start’ signal (again, now an edge) to pass to the VDL 12. Now, the initialization logic 50 sets EP to a maximum value, such that the ‘start’ signal now enters the first (left most) stage in the VDL 12. (Alternatively, in embodiments in which the exit point varies, the exit point would be set all the way to the right most stage). Thereafter, the ‘start’ signals runs through the stages of the VDL 12 where it is then captured as explained below in reference to the ‘stop’ clock pulse.
However, prior to discussing the ‘stop’ clock pulse, we can see that the time it takes for the ‘start’ signal to get to the start of the VDL 12, i.e., from point (A) to point (B), is:Start signal from (A) to (B)=Tref+Tmeas+Tid+Tmodel+Tfb+Tlatch+Tmeas  (Eq. 3)
The ‘stop’ clock pulse also begins at point (A), but uses a later clock pulse some N cycles after the pulse used as the ‘start’ clock pulse discussed above. This later clock pulse does not pass through the VDL 12, but instead goes directly to point (C) through Tref delay 20a, to latch 22b (where it is converted to an edge), and to strobe circuitry 24. Because the ‘stop’ signal starts some N*Tck after the ‘start’ signal, the time it takes for the stop signal to transgress its route is:Stop signal from (A) to (C)=N*Tck+Tref+Tlatch+Tstrb  (Eq. 4)
As noted above, the point of the ‘stop’ signal is to capture the ‘start’ clock pulse as it eventually transgresses through the VDL 12. This is illustrated in FIG. 3. As shown, the VDL 12 is formed of several stages 40a-40h, each connected to a latch 42a-h. When the ‘stop’ signal (C) is asserted, the ‘start’ signal (B) which has otherwise been propagating through the stages 40a-h of the VDL is captured using the stop signal as the latches' control signal. This captured value provides a measurement of Tvd1 (Tvd1(meas)) that should approximately meet the lock condition of Equations (1) and (2), and this measurement is expressible as a number of VDL stages 40. For example, and as the chart in FIG. 3 shows, should the ‘start’ signal only propagate through one stage 40a before being captured by the ‘stop’ signal, this suggests the Tvd1 should initially be set to a low value—i.e., one VDL stage 40h—to meet the lock condition. In other words, based on such a measurement, the initial entry point (EP) for the input clock into the VDL 12 would occur at VDL stage 40h. If the ‘start’ signal propagates through two VDL stages 40a and 40b before being captured, then Tvd1 would need to comprise two VDL stages. In other words, the initialized entry point (EP) would be chosen as 40g, such that the input clock would initially pass through two delay stages 40g and 40h in the VDL 12. (In embodiments in which the exit point varies, the captured ‘start’ signal would not need to be “flipped” as the initialized point in the VDL 12: For example, if the ‘start’ signal propagates through two VDL stages 40a and 40b before being captured, then Tvd1 would need to comprise two VDL stages, and the initialized exit point would be chosen as 40b).
To summarize, this initialization measurement technique allows the entry point (EP) (or exit point in such embodiments) into the VDL to be initially set at a value generally corresponding to the lock condition of Equations (1) and (2). However, this measurement has its shortcomings.
The measured delay, Tvd1(meas), equals the difference between the stop and start signals:Tvd1(meas)=Stop−StartTvd1(meas)=N*Tck+Tstrb−Tid−Tmodel−Tfb−2*Tmeas  (Eq. 5)
As one might expect, the measured Tvd1(measured) will differ from the ideal Tvd1(ideal), and this difference can be quantified as error. Using Equations (2) and (5), and noting that Tmodel is designed to equal Td1+Td2, this error can be computed as follows:Error=Tvd1(meas)−Tvd1(ideal)=N*Tck+Tstrb−Tid−Tmodel−Tfb−2*Tmeas−[N*Tck−(Td1+Tid+Td2)]=Tstrb−Tfb−2*Tmeas  (Eq. 6)
Tstrb and 2*Tmeas are static, and can be trimmed out of the measurement using tuning delays. Tfb is variable, and as noted earlier can be used to decrease Tac. However, despite being variable, Tfb is also known to the device, and can likewise be trimmed out of the measurement. In other words, to the extent delays in Tstrb, Tfb, and Tmeas exist as error in Equation (6), they can be accounted for to mitigate error in the measurement, and to initialize the entry point (EP) of the VDL 12 to an appropriate number of stages to achieve a lock.
However, to the extent Tref is used to increase Tac, the measurement technique as just described will not be aware of such an adjustment. This is because the error term of Equation (6) is not a function of Tref, and hence it cannot be known to what extent Tref will cause Tvd1 as measured, Tvd1(meas), to deviate from the ideal, Tvd1(ideal). Accordingly, no adjustment to the number of VDL stages 40 can be made to compensate for the programmed delay in Tref. Instead, the DLL 10 must perform a gradual iterative adjustment of the entry point (EP) (or exit point) after initialization, which increases DLL lock time.
More troubling, such unawareness of the trimmed value Tref increases the possibility that the DLL 10 will shift the input clock, ClkIn, in the wrong direction to establish a lock. This is likely to happen, for example, if the trim to Tref is greater than half of the clock period, Tck, which might occur due to process deviations or design changes that are not reflected in the delay model 14. Again, this is time and power consuming, and increases the jitter-related error. Moreover, as clock speeds increases, i.e., as Tck shrinks, the possibility of non-optimal initialization is becoming more problematic.
The art would be benefited by improved methods and circuitry for the initialization of a DLL architecture, and this disclosure provides such a solution.